Interrupt Acknowledge Bus Cycle Timing - Motorola M68060 User Manual

MISCELLANEOUS
ATTRIBUTES
UPA1–UPA0
SIZ1–SIZ0
TM2–TM0
Figure 7-28. Interrupt Acknowledge Bus Cycle Timing
Note that the acknowledge termination ignore state capability is applicable to the breakpoint
acknowledge cycle. If enabled, TA, TEA, and TRA are ignored for a user-programmed num-
ber of BCLK cycles.
MOTOROLA
C1 C2
BCLK
A31–A0
TT1–TT0
BYTE
R/W
INTERRUPT LEVEL
BS2–BS0
BS3
CIOUT
TS
TIP
SAS
TA
AVEC
D31–D8
VECTOR #
D7–D0
INTERRUPT
ACKNOWLEDGE
M68060 USER'S MANUAL
Bus Operation
C1 C2
WRITE STACK
7-37