Locked Bus Cycle For Tas Instruction Timing - Motorola M68060 User Manual

Bus Operation
BCLK
A31–A2
A1–A0
MISCELLANEOUS
ATTRIBUTES
R/W
SIZ1–SIZ0
BS3–BS0
CIOUT
LOCK
LOCKE
SAS
D31–D0
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
Figure 7-23. Locked Bus Cycle for TAS Instruction Timing
recognized asserted, the processor ignores the data and appends a wait state instead of
terminating the transfer. The processor continues to sample TA on successive rising edg-
es of BCLK until TA is recognized as asserted. The registered data is then passed to the
appropriate memory unit. If more than one read cycle is required to read in the operand(s),
C1 and C2 are repeated accordingly.
7-30
C1 C2
LONG
TS
TIP
TA
LOCKED TRANSFER
M68060 USER'S MANUAL
CI C3
PRE
DRIVE
C4
MOTOROLA