Snooped Bus Cycle - Motorola M68060 User Manual

BUS
ARBITRATION
STATE
BCLK
SNOOP
A31–A0
TRANSFER
ATTRIBUTES
TT1
TS
TA
D31–D0
BR
BG
BB
BTT
AM_BR*
AM_BG*
* AM indicates the alternate bus master.
7.13 RESET OPERATION
An external device asserts the reset input signal (RSTI) to reset the processor. When power
is applied to the system, external circuitry should assert RSTI for a minimum of ten BCLK
cycles after V is within tolerance. Figure 7-48 is a functional timing diagram of the power-
CC
on reset operation, illustrating the relationships among V
signals. CLK is required to be stable by the time V
ification. CLK should start oscillating as V
internal to the part caused by the random manner in which internal flip-flops power-up. RSTI
is internally synchronized for two BCLKs before being used and must meet the specified
MOTOROLA
END-TEN AM-IMP SNOOP
C1 C2 C3
Figure 7-47. Snooped Bus Cycle
CC
M68060 USER'S MANUAL
AM-EXP AM-EXP AM-EXP
C4 C5 C6
ALTERNATE
MASTER
, RSTI, mode selects, and bus
CC
reaches the minimum operating spec-
CC
is ramped up in order to clear out contention
Bus Operation
PROCESSOR
7-71