Integer Unit; Instruction Fetch Unit; Mc68060 Block Diagram - Motorola M68060 User Manual

Introduction
The architecture of the MC68060 processor is implemented in the following major blocks:
• Execution Unit

—Instruction Fetch Unit

—Integer Unit

—FPU
• Memory Units
—Instruction Memory Unit
• Instruction ATC
• Instruction Cache
• Instruction Cache Controller
—Data Memory Unit
• Data ATC
• Data Cache
• Data Cache Controller
• Bus Controller
These major units execute concurrently to maximize sustained performance. Note that the
caches reside on separate buses allowing concurrent instruction fetch, data read, and data
write operations (internal Harvard architecture).
EXECUTION UNIT
INSTRUCTION FETCH UNIT
BRANCH
CACHE
pOEP
DECODE
FLOATING-
POINT
EA
UNIT
CALCULATE
OC
EA
EA
FETCH
FETCH
EX
FP
INT
EXECUTE
EXECUTE
DATA AVAILABLE
WRITE-BACK
1-6
IAG
IA
CALCULATE
IC
INSTRUCTION
FETCH
IED
EARLY
DECODE
IB
INSTRUCTION
BUFFER
sOEP
DS DS
DECODE
AG AG
EA
CALCULATE
OC EA OC
FETCH
EX INT EX
EXECUTE
INTEGER UNIT
DA
WB
OPERAND DATA BUS
Figure 1-1. MC68060 Block Diagram
M68060 USER'S MANUAL
INSTRUCTION INSTRUCTION
ATC CACHE
INSTRUCTION
CACHE
CONTROLLER
INSTRUCTION MEMORY UNIT
DATA
CACHE
CONTROLLER
DATA DATA
ATC CACHE
DATA MEMORY UNIT
ADDRESS
B
U
S
C
O
N
DATA
T
R
O
L
L
E
R
CONTROL
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