Line Write Bus Cycle Timing - Motorola M68060 User Manual

Bus Operation
MISCELLANEOUS
ATTRIBUTES
SIZ1–SIZ0
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
sertion and terminates the line write bus cycle, TIP remains asserted if the processor is
ready to begin another bus cycle. Otherwise, the processor negates TIP during the next
clock. The processor also three-states the data bus during the next clock following termi-
nation of the write cycle.
7.7.5 Locked Read-Modify-Write Cycles
The locked read-modify-write sequence performs a read, conditionally modifies the data in
the processor, and writes the data out to memory. In the MC68060, this operation can be
indivisible, providing semaphore capabilities for multiprocessor systems. During the entire
7-28
C1 C2
BCLK
A31–A4
A1–A0
R/W
BS3–BS0
CIOUT
CLA
A3–A2
01
TS
TIP
SAS
TA
TBI
PRE
D31–D0
DRIVE
Figure 7-22. Line Write Bus Cycle Timing
M68060 USER'S MANUAL
C3 C4 C5
10 11 00
MOTOROLA