Table of Contents
Advertisement
Architectural Overview
1.3.3 Arc Four Execution Unit (AFEU)
The AFEU accelerates an algorithm compatible with the RC4 stream cipher from RSA
Security, Inc. The algorithm is byte-oriented, which means a byte of plaintext is encrypted
with a key to produce a byte of ciphertext. The key is variable length, and the AFEU
supports key lengths from 40 bits to 128 bits (in byte increments), providing a wide range
of security strengths. RC4 is a symmetric algorithm, which means each of the two
communicating parties share the same key.
The AFEU module accepts data in 32-bit words per write cycle and produces 4 bytes of
ciphertext for every 4 bytes of plaintext. Key material is first written to the AFEU module
which performs the initial permutation on the key, after which processing on 32-bit words
can begin.
1.3.4 Message Digest Execution Unit (MDEU)
The MDEU is capable of performing MD4, MD5, and SHA-1, three of the most popular
public message digest algorithms. At its most basic level of operation, the MDEU receives
16 32-bit words containing a message or partial message, computes for 48, 64, or 80 cycles
(depending on the algorithm selected), and produces a hashed message of 128 bits for
MD4/MD5 and 160 bits for SHA-1. The MDEU also includes circuitry to automate the
process of generating a Hashed Message Authentication Code (HMAC) as specified by
RFC 2104. The HMAC can be built upon any of the hash functions supported by the
MDEU.
1.3.5 Random Number Generator (RNG)
The RNG is a digital integrated circuit capable of generating 32-bit random numbers. It is
designed to comply with FIPS-140 standards for randomness and non-determinism.
Because many cryptographic algorithms use random numbers as a source for generating a
secret value, it is desirable to have a private RNG for use by the MPC180E. The anonymity
of each random number must be maintained as well as the unpredictability of the next
random number. The private RNG allows the system to develop random challenges or
random secret keys. The secret key can thus remain hidden from even the high-level
application code, providing an added measure of physical security.
1.3.6 Interrupt Controller (IRQ)
The Interrupt Controller manages hardware interrupts generated by individual execution
units into a maskable interrupt, IRQ. Multiple internal interrupt sources are logically ORed
to create a single, non-prioritized interrupt output for the processor. The controller lets the
host read unmasked interrupt source status as well as the request status of masked interrupt
sources. This allows a given unmasked interrupt source to generate an interrupt request to
the processor.
Chapter 1. Overview
1-5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Advertisement
Table of Contents
