HP 3000 III Series Manual page 92

System/CPU Overview
2-117. CARRY FLIP-FLOP (CRRY). The Carry flip-flop controls the
status word carry bit (bit 5) and stores the state of the Carry
signal from the ALU when the OFCENB signal is true. The Carry
flipflop is set and cleared by Special field codes SCRY and CCRY
respectively. Refer to paragraph 2-45.
2-118. CONDITION CODE LOGIC (CeO AND CCl). The condition code
logic controls the condition code. Refer to paragraph 2-46.
2-119. PRE-ADDER. The Pre-Adder is used to gain a speed in-
crease for instructions that use or perform computations on CIR
bits. For example, when executing indexed memory reference in-
structions (not indirect), the proper CIR displacement field is
pre-added to the X Register contents. Therefore, the final abso-
lute address can be computed in only one clock cycle by adding
the output of the Pre-Adder to the contents of the base register
(PB, DB, Q,
or
Z).
2-120. R-BOS REGISTER. The R-Bus Register is a 16-bi t register
that provides buffer storage between the R-Bus and the ALD. The
R-Bus Register can be left-shifted one bit position (refer to
Function field code QASL, Section
V)
and is loaded from the
R-Bus. Refer to R-Bus field code definitions.
2-121. S-BUS REGISTER. The S-Bus Register is a 16-bi t
that provides buffer storage between the S-Bus and the
S-Bus Register can be r igh t- shifted one bi t posi tion
Function field code QASR, Section
V)
and is loaded
S-Bus. Refer to S-Bus field code definitions.
register
ALD. The
(refer to
from the
2-122. ALU. The ALU combines the R- and S-Bus data and gener-
ates functions that are divided into two modes or groups; arith-
metic functions and logic functions. The 16-bit output of the
ALU is placed on the T-Bus for either the Shifter or Decimal
Corre ctor .
2-123. SHIFTER. The Shifter performs all shifts and rotates (left
shift, right shift, right-left swap, etc.) on the T-Bus data as
directed by the Shift Field Decoder. The output of the Shifter
is placed on the U-Bus for storage in one of the U-Bus registers.
2-124. DECIMAL CORRECTOR. The Decimal Corrector adds six to each
group of four bits in the output from the ALU and generates car-
ries to the next group as required to yield a correct decimal
addition. Each group of four bits in the source operands must be
in the range of 0 to 9. If an invalid digit is detected during
the add cycle, overflow will be true.
2-125. ADDRESS COMPUTER OUTPUT REGI STER (ACOR). The ACOR is a 16-
bit register that functions as a memory address buffer between
the U-Bus and the CTL Bus.
2-126. DATA COMPUTER OUTPUT REGISTER (DCOR). The DCOR is a 16-
bit register that functions as a buffer for memory bound data and
operand address transfers between the U-Bus and the CTL Bus.
2-60