HP 3000 III Series Manual page 241

MCU/Main Memory Overview
Check bit CO is instrumental in detecting double-bit errors.
Double-bit errors are logged, but a unigue address is not gener-
ated for each double-bit error pair and errors are n9t corrected.
Instead, bad parity is generated on theCTL Bus requesting the
receiving module to flag the error. The MCL PCA includes logic
circuits to detect double errors and to force bad CTL Bus parity.
The MCL peA also includes logic circuits to log an error in the
Error Logging Array (ELA) during read operations.
For diagnostic purposes, the
SMA
PCA(s) can be programmed through
the FLI PCA to disable write error correction. The check bits
write control logic can be disabled during a write operation to
allow data bits to be changed without modifying the check bits.
Error correction is always enabled during read operations. All
detected errors are recorded regardless whether they are single
bit or mUltiple bit. Each single-bit detected error is logged
according to chip location in the ELA. The ELA uses static a lK
RAM located on the MCL PCA. Five bits of memory address and five
bits of error code determine the error logging address in which a
"1" is stored in the ELA.
The lK RAM is organized as a 1024 x 1 bit array requiring 10 bits
of address. The five most significant bits of ELA address cor-
respond to the five most significant bits of memory address; two
bits define one of four
SMA
PCA's and three bits define one of
eight rows of chips on the particular
SMA
PCA. The five least
significant bits define one of 22 chips in a particular row and
correspond to the error code HOI through H05. Refer to figures
6-5 through 6-7. The
ELA
can be read under program control by
means of the FLI PCA. Any ELA location containing a "1" signi-
fies that an error was detected. The location of the faulty chip
can be found by using the 5-bit .octal address portion of the ELA
address and then looking up the bit in the conversion table of
figure 6-7.
6-39. MEMORY ERROR LOGGING FACILITY. The memory error logging
facility permits the system's user to examine the error history
of Main Memory. The facility consists of the following elements.
a. Error correcting memory and the FLI PCA
b. Memory error logging system process (MEMLOGP)
c. Memory error log analysis program (MEMLOGAN)
d. Memory error logging internal update program (MEMTIMER)
Memory error logging is in no way connected to or related to
standard system logging. Both function independently. None of
the operator interfaces to system logging have an effect on mem-
ory logging. Memory error logging will always be invoked if er-
ror correcting memory is present in the system. MEMLOGP is a
system process that runs under MPE. Once initiated, MEMLOGP
automatically and periodically interrogates the FLI PCA to obtain
the latest error information. MEMLOGP is activated during the
6-17