HP 3000 III Series Manual page 39

System/CPU Overview
A Device Controller consists of one or more peA's and, depending
on the particular type of controller, can drive one or several
exte rnal I/O devices. There are three types of Device Control-
lers; controllers used only for direct I/O, controllers used only
for programmed I/O, and controllers used for both direct and pro-
grammed I/O. Regardless of the type, every Device Controller can
accept all or some direct I/O instructions, can generate inter-
rupts, and has a unique device number for addressing. Device
Controllers can be installed in any of the available card cage
slots designated in tables 1-1 through 1-3.
2-15. eTl
Bus Priority
All computer system modules contain MCU logic that interfaces
each module to the others via the CTL Bus. Each module gains
access and control of the CTL Bus on a priority basis via its MCU
logic. (The CTL Bus is only available to one module at a time.)
For example; if two modules attempt to gain access to the CTL Bus
simultaneously, the module with the higher priority will get the
bus and the module with the lower priority will not get the bus
until it is released by the higher-priority module. CTL Bus
prior ity is resolved by assigning prior ity numbers to each system
module with jump er sw itches loca ted in each mod ule ' s MCU logic.
The system modules assigned the lowest priority numbers have the
highest priority for accessing the CTL Bus.
Figure 2-2 illustrates the CTL Bus priority number assignments
for each module in a typical computer system. It should be noted
that the highest CTL Bus priorities (lowest priority numbers) are
reserved for Main Memory and that the lowest CTL Bus priority
(priority number 5) is reserved for the Central Processor Module.
The lower memory module responds to both prior ity numbers 0 and
1. The upper memory module responds to both priority numbers 2
and 3. The required MCU logic for Main Memory is contained on
the MCL PCA(s). (Priority for Memory Banks 0 through 7 is con-
trolled by one MeL PCA and priority for Memory Banks 8 through 15
is controlled by a second MCL PCA.) If installed, the selector
Channel(s) has the next highest CTL Bus priority (priority number
4) after Main Memory. The required MCU logic for the selector
Channel(s) is contained on the Port Controller PCA. As previous-
ly discussed, the Central Processor's MCU resolves CTL Bus prior-
ity conflicts between the lOP and
cpu.
The lOP always has higher
priority than the CPU. Therefore, the CPU always has a lower CTL
Bus priority than any other module in the computer system.
2-16. OPERATING ENVIRONMENT
2-17.
Virtual Memory
Virtual memory is a memory management scheme that uses semicon-
ductor Main Memory and disc storage secondary memory. Due to a
technique called memory segmentation, many programs stored in
secondary memory can concurrently access the computer system and
~hare its Main Memory. The system organizes programs into vari-
able-length segments of code and data in secondary memory which
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