HP 3000 III Series Manual page 272

I/O System
7-15. lOP CONTROL. The lOP control block represents sequencing
logic for transfers between the device and memory, and between
the device and the CPU. Each of the 1 ines shown ente ring or
leaving this block are discussed with their associated transfer
sequences.
7-16. INTERRUPT CONTROL. The interrupt control logic accepts
an Interrupt Request (INTREQ) from the Device COntrollers on the
lOP Bus, interrogates the Device Controllers with INTPOLL to find
the highest-priority request, and, when Interrupt Acknowledge
(INTACK) is received, loads the device address into the lOA Reg-
ister.An External Interrupt (EXTlNT) signal is issued to the
cpu.
7-17. INT OEVNO. The I/O Address (lOA) Register holds the
device number of the interrupting device so that, upon command,
the CPU can read the contents onto the S-Bus for interrupt
pr oces sing.
are two data output
for memory data received
Register for direct data
Signals from lOP control
the lOP Bus or transfer the
entr y.
7-18. DATE OUTPUT REGISTERS. There
reg i ste r s, the lOP Oa ta Out Registe r
from the CTL Bus, and the
100
Data Out
received via the U-Bus from the CPU.
can either read the contents out onto
contents into MUX for restoring a DRT
7-19. DATA INPUT REGISTERS. There are two input registers. The
lOP Data In Register is used for sending data to memory via the
CTL Bus. This register is loaded from either the lOP Bus or, for
DRT entry restoring, from the lOP Data Out Register. When doing
a ORT store, the lOP Da ta In Registe r is incremented by two be-
fore the transfer is made. The second input register, IOD Data
In, may be used either as a direct data input register or as a
memory address register. It is loaded from the lOP Bus. During
direct I/O execution, the register contents are read onto the
cpu
S-Bus. When addressing memory, the register contents are read
out to the CTL Bus.
7-20. Module Control Unit
As previously discussed in Sections II and VI, the Module Cbntrol
Unit (figure 6-1) contains MCUs for both the CPU and the lOP.
The MCUs operate basically in parallel, but not independently.
Since both MCUs share the same access to the CTL Bus, and also
share the same module number, it is necessary to resolve priority
when both' the lOP and CPU simultaneously attempt to use the bus.
Priority is resolved so that lOP requests take precedence over
CPU requests except that a CPU high request takes precedence over
an lOP low request. This exception means that the CPU is in the
middle of a memory write operation, having sent an address to
memory, and the high request is an attempt to follow up by send-
ing the data. CPU low request represents the beginning of a
transfer (attempt to send an address) and any lOP request will
have priority over the CPU low request.
7-1R