HP 3000 III Series Manual page 35

System/CPU Overview
2-6. PORT CONTROLLER BUS. The Port Controller Bus (not shown
in figure 2-1) provides the communication path between each
Selector Channel and the Port Controller which interfaces with
the CTL Bus. This bus consists of a 50-conductor flat cable and
connectors and connects each Selector Channel to the Port
Co ntroller •
2-7. MULTIPLEXER CHANNEL BUS. Except for minor signal nomen-
clature differences, the MUltiplexer Channel Bus (one per Multi-
plexer Channel) is identical to the Selector Channel Bus. This
allows certain high-speed I/O devices to be connected inter-
changeably to either bus. The major difference is that data
transmissions are under control of a Multiplexer Channel instead
of a Selector Channel. All data transmissions in this case are
via the lOP Bus and are multiplexed among the I/O devices on a
word-by-word basis. (The equivalent data lines on the selector
Channel Bus are used as service request lines on the Multiplexer
Channel Bus.) This bus consists of a 50-conductor flat cable and
connectors and connects each Multiplexer Channel to each of its
a s soc i a te d
De
vice Co n tr 011 e r s •
2-8. POWER BUS. The Power Bus (not shown in figure 2-1), unli ke
the previously discussed flat-cable buses, is a rigid PCA with
fixed 56-pin connectors. The Power Bus provides dc power and and
some lOP Bus related signals for each PCA mounted in a particular
card cage module. There is one Power Bus for each card cage mod-
ule and each Power Bus is individually wired to the computer's
power supply. Although dc power is not distributed from card
cage module to card cage module via the Power Bus, a 20-conductor
flat cable is connected be tween the Power Buses for the distr ibu-
tion of the lOP Bus related signals. In addition, each Power Bus
contains connector pins reserved for the data poll, interrupt
poll, and system clock s.ignals.
2-9. Functional Hardware Elements
Brief descriptions of the principal hardware elements illustrated
in figure 2-1 are contained in paragraphs 2-10 through 2-14.
2-10. CENTRAL PROCESSOR MODULE. The Central Processor Module
determines the basic characteristics of the computer system's
hardware and consists of the MCU, CPU, and lOP. Significant
features of the module are listed in table 2-1.
The MCU resolves CTL Bus priority conflicts between the CPU and
lOP and interfaces both to the CTL Bus. Refer to paragraph 2-15.
A detailed discussion of the MCU is contained in section VI.
The CPU translates received instruction words into microprogram
starting addresses, decodes microprograms into fixed control sig-
nal sequences, executes various ar ithmetic functions, and either
transfers the results out of the Central Processor Module or
stores the results in various internal registers for future use.
The CPU shares the MCU with the lOP. A detailed discussion of
the CPU is contained in paragraphs 2-71 through 2-133.
2-3