HP 3000 III Series Manual page 70

indirect addressing.) For most
2-34), indirect addressing is
System/CPU Overview
tion word. (A logic 1 specifies
branch instructions (paragraph
spe c if ie d b Y bit 4.
2-51. CODE INDIRECT. Both P+ and P- examples of ind irect ad-
dressing in a code segment are shown in figure 2-15. The first
example shows the actions occur ing for an assumed "LOAD P+4, I"
instruction. The displacement (+4) points to the Indirect Cell
at P+4. The Indirect Cell contains a +3 self-relative address.
This points to a location three addresses higher, or P+7. It is
the contents of ,P+7 that will be loaded onto the TOS by the "LOAD
P+4, I" instr uction. The second example shows the actions occur-
ing for an assumed "LOAD P-4, I" instruction. The displacement
(-4) points to the Indirect Cell at P-4. The Indirect Cell con-
tains a -3 self-relative address. This points to location P-7
which is the effective address for th "LOAD P-4, I" instruction.
2-52. DATA INDIRECT. The first example in figure 2-15 of indi-
rect addressing in a data segment shows the actions occuring for
an assumed "LOAD DB+4, I" instruction. The displacement (+4)
points to the Indirect Cell at DB+4. The Indirect Cell contains
a DB+7 relative address. This is not a self-relative address
and, therefore, the effective address is at location DB+7. It
should be noted that it is possible for the effective address to
be below as well as above the Indirect Cell. The second example
shows the actions occuring for an assumed "LOAD Q+4, I" instruc-
tion. The displacement (+4) points to the Indirect Cell at Q+4.
The Indirect Cell contains a DB+7 relative address and, therefore,
the effective address is again at location DB+7. The third ex-
ample shows the actions occur ing for an assumed "LOAD S-4, I" or
"LOAD Q-4, I" instruction. The displacement (-4) points to the
Indirect Cell at either S-4 or Q-4 depending on the instruction
and, since the contents of the Indirect Cell is assumed to be+7,
the effective address for both instructions is again DB+7.
2-53. Indexing
The memory address instructions (paragraph 2-44) use indexing to
modify an operand address. Indexing is specified by bit 4 of the
instruction word. (A logical 1 specifies indexing.) Figure 2-16
shows examples of indexing when combined with positive and neg-
ative addressing modes (both direct) and an example of indirect,
indexed addressing (positive mode only) for both code and data
segments. It should be noted that in each example, the index is
assumed to be 5. This is established by the "LDXI5" instruction
that preceds each LOAD instruction used in the examples. This
instruction loads the value 5 in the Index Register (X Register).
2-54. CODE INDEXING. The first example in figure 2-16 shows the
actions occuring for an assumed "LOAD P+4, X" instruction. The
displacement (+4) would by itself point to location P+4. How-
ever, by adding the index of 5 to the displacement, the location
P+ll (octal) is addressed. It is the contents of this location
tha twill be loaded onto the TOS by the "LOAD P +4, X" instr uc-
tion. The second example shows the actions occuring for an
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