HP 3000 III Series Manual page 230

MCU/Main Memory Overview
6-10. Store An Operand Operations
The operations for storing an operand in memory involves much the
same logic operations that were discussed in the preceding fetch
transmissions. The main difference is that instead of a CPU to
memory transmission and then a memory to CPU transmission, there
are two consecutive transmissions from CPU to memory. The first
transmission is the address and the second is the operand. The
following paragraphs are again condensed to illustrate only the
overall flow of information.
6-11. CPU ADDRESS TRANSMIT. A signal from the ROM Store field
loads the U-Bus contents into the ACOR Register on the CPU and
sets the LREQ (low request) flip-flop on the MCU. (See figures
2-20 and 6-1.) The MCU Operation Encoder gives a memory opcode to
the MOP Register. In this c~se, the opcode is write rather than
Read as in the previous cases. (Neither the NIP nor OPIND flip-
flops are set.) After checking to see if the destination module
is ready and the Enable (ENB) signals are present, the LREQ sig-
nal sets the Select flip-flop which causes the address to be read
out to the CTL Bus.
6-12. MEMORY RECEIVE. The memory module (figure 6-2) after recog-
nizing its TO code and setting the Ready fl ip-flop, locks the ad-
dress from the CTL Bus into the Address Register. The FROM, MOP,
and Address Registers remain locked and the ROY line goes low so
that no other module can send a new address to this memory
module.
6-13. CPU DATA TRANSMIT. Meanwhile, the CPU has put the operand
on the U-Bus, and a DATA signal from the ROM Store field loads it
onto the CPU DCOR (figure 2-20) . The DATA signal also sets the
High Request (HREQ) flip-flop on the MCU (figure 6-1). Destina-
tion readiness does not need to be checked, however, since memory
is expecting a data transmission from this module. After prior-
ity checks, the HREQ signal sets the CPU Select flip-flop which
reads out the operand to the CTL Bus. (The memory opcode is NOP,
since memory is already holding the appropriate opcode.)
6-14. MEMORY RECEIVE. In the memory module the TO Comparator
recognizes its TO code and the FROM Comparator verifies trans-
mission from the correct module. The true ouputs from both of
these comparators cause the operand from the bus to be loaded
into the Wr ite Data Register and cause the memory timing to start
the memory write cycle. This causes the operand to be stored
into the addressed location.
6-15. Command A Module
The machine instruction set include's a Command (CMD) instruction
that permits privileged mode programs to issue commands directly
to a module (assuming the module is equipped to handle such com-
mands). When programmed, the CMD instruction takes a l6-bit word
from the TOS and sends it to a module whose module number (and
6-6