Second Level Interrupt Or Dispatcher Interrupted - HP 3000 III Series Manual

I nte r r upt Sys tern
1CS
Set during execution of DISP instruction
Reset during execution of IXIT or PSEB
instructions.
Set by microcode if Dispatcher
was interrupted.
~
01
&1
~O (G)
D
DB-Bank
D DB
First INT DEVNO
~~ .~
D
C
B
A
X
~P
I
STATUS
a
81
~o
../"
DB-Bank
DB
Second INT OEVNO
Figure 8-4. Second Level Interrupt or Dispatcher Interrupted
g. The CPU obtains the device number from the Interrupt Address
Register in the
lOP
and calculates the address of the DRT
entry. DB is set to the DBI value in the third word of the
DRT entry (7).
h. The Status Register (8) is set to privileged mode, external
interrupts enabled (%140000).
i. The DB-Bank Register (9) is set to O.
j. The S Register is set to point at location Q+3 (10) and the
device number of the interrupting device is stored into this
location. At this point, the ICS is fully delimited by reg-
ister values and is ready for handling interrupt data.
k. The external program label for the interrupt receiver code is
fetched from the second word of the DRT entry. The CST entry
is obtained from the segment number in the external program
label. Then, the PB-Bank Register (11) is set based on the
CST entry.
1. The PB Register (12) is set based on the CST entry.
m. The PL Register (13) is set based on the CST entry.
8-11