HP 3000 III Series Manual page 249

MCU/Main Memory Overview
CIO
I I
I I I
I
0 1 2 3 4 5 6
718
9 10 11
12
13 14 15
1
MST.CL.,~
MSB
LSB
NOT USED
\.
)
READ COpy
Y
10 BIT ADDRESS
READ SCAN
DISWEC
L/U512K
Figure 6-11. CIO Word Format
Bit 3 Read Scan. The I/O Logging Array contents are inter-
rogated starting at the address specified by bits 6
through 15 and finishing at address %1777. The scan
is completed when the Address Counter rolls over to
%0000. The scan will halt at any I/O Logging Array
location containing an error. An RIO instruction may
be executed to retrieve the address of that error lo-
cation. After the RIO completion, the scan will re-
sume. During a scan, TIO bit 1
=
0 (R/W not OK) and
goes to a 1 two usec after a halt on error or a scan
completion. A read scan can be aborted by a Master
Clear.
Bit 4 DISWEC. The Disable Write Error Correction flip-flop
is set on the FLI PCA resulting in a memory operation
with the error correction logic disabled. During a
write operation, the data bits can be changed without
modifying check bits C8 through C5. Note that error
correction is disabled on all MCL PCA's. Bit 4 can be
cleared by I/O Reset, PFW, PON, completion of a Read
Copy or Write Copy (WIO instruction), CIO Master
Cl ear, or se t ting bit 4 to a O.
Bit 5 L/NU 512K• I fbi t 5
=
1, th en the up pe r 512 K Err or
Logging Array is selected. If bit 5
=
0, then the
lower 5l2K Error Logging Array is selected. The
upper or lower 5l2K Error Logging Array is selected
after one CPU clock cycle.
Bits 6-15 Address. The 10 bit address (1024 locations) is the
starting address for a Read Copy of the Error Logging
Array to the I/O Logging Array or a Read Scan of the
I/O Logging Array. The address is loaded on all CIO
instructions and is not affected by Master Clear.
6-25