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Machine Instructions and Stack Operations
1.
STT #34; ASS DST - Absent Data Segment.
The absence
bit
in
the DST entry for the referenced segment is set.
4-3. CONDITION CODE
Bits 6 and
7 of the CPU Status Register are used for
the condi-
tion code.
Although several instructions make special use of the
condition code, the condition code typically indicates the
state
of
an
operand
(or a comparison result with two operands).
The
ope rand may be a byte,
word,
doubleword,
tr ipleword,
or quad-
rupleword
and may be located
on
the TOS,
in the Index Register,
or in a specified memory location.
Refer to paragraph 2-46
for
condition code interpretations.
4-4. INSTRUCTION FORMATS
The machine instruction formats are shown in figures 4-1
through
4-5.
For a general discussion
of the formats,
refer to para-
graph 2-30.
4-5. INSTRUCTION DEFINITIONS
Paragraphs 4-6 through 4-15 contain definitions for 36 of the 191
machine instructions.
The definitions are arranged
in mnemonic
alphabetical order
within each of the
instruction groups.
When
additional information
is required to fully define a
particular
instruction,
an Instruction Commentary number
reference is made
immediately following
the
instruction's
definition.
In
such
cases,
refer to the corresponding reference number
in paragraph
4-16.
Also,
some of the instruction
definitions
refer to
the
first five elements of the stack as A, B, C, D, and
E.
With this
convention, A is the TOS (8), B is S-l, C is S-2, D is S-3, and D
is S-4.
4-6. Stack Op Instructions
ADD
Add
If
Alternate
POSition
The top two words of the stack are added in integer form and
are
then deleted.
The resulting sum is pushed onto the stack.
Stack opcode: 20
Indictors: CCA, Carry, Overflow
Traps: STUN, ARITH
4-3
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