HP 3000 III Series Manual page 329

Interrupt System
the external program label (8), thus transferring control to
the interrupt receiver code.
8-51. INTERRUPT HANDLER
The Interrupt Handler is a microprogram (actually a set of micro-
programs) permanently stored within a read-only memory in the
CPU. The CPU periodically checks for the existence of a waiting
interrupt condition which is stored in one of several bit posi-
tions in a dedicated CPU register (CPXI or CPX2), and then trans-
fers control to the Interrupt Handler. The purpose of the
Interrupt Handler is to save the interrupted environment and
transfer control t~ the interrupt routine in software. The sus-
pended environment is saved in a format that is ready to resume
execution. ~he descriptions that follow are essentially a sum-
mary of the preceding portion of this section. Figure 8-7
illustrates the operations performed by the Interrupt Handler.
Generally, the sequence beg ins with the STAR!' block at the top
left corner and ends with the NEXT CPU INSTRUCTION block at the
bot tom right cor ner.
8-52. DISP Instruction
The DISP instruction calls the Dispatcher which is a system pro-
cess whose primary function is determining which active process
will use the CPU and then transfer control to that process. The
Dispatcher can be called from a user program if in privileged
mode. For example, the last instruction of a user process is a
PCAL to a sys tern process called TERMINATE' which, among othe·r
things, cleans up the CST, DST, and PCB entries for the user pro-
cess. TERMINATE' then issues a DISP instruction. Some system
error handling routines such as trap handlers may use it to call
the Dispatcher after aborting the user program. The DISP in-
struction can be executed by an Interrupt Handler after servicing
all pending interrupts from a multiple device controller. In
this case, the Dispatcher is not actually called, but instead a
condition code of CCG is set and bit 0 of QI is set to instruct
the IXIT instr uction what to do. The next CPU instr uction after
the DISP instruction would then be executed and the Interrupt
Handler would execute the IXIT instruction. The IXIT instruction
then uses bit 0 of QI to determine which path to take. All pro-
grams which use the DISP instruction must be prepared to handle
the condition of the Dispatcher being pseudo disabled. (Refer to
paragraph 4-16, 7.)
8-53. Pseudo Enabling/Disabling .The Dispatcher
The PSDB (Pseudo Disable) and PSEB (Pseudo Enable) instructions
are used to pseudo disable and enable the Dispatcher. (Refer to
paragr aph 4-16; 7.) The two instr uctions must be executed in
pairs; for each disable, there ID.USt be a corresponding enable
within the same .process. The Dispatcher can be locked several
levels deep with PSDB instructions, but must have one PSEB to
unlock each level. A count is maintained in QI-18 for the number
of disables which have not been unlocked. These instr uctions are
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