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I/O System
7-32.
Selector Channel Transfers.
A Selector Channel
transfers
data from many sources in a data block manner.
That is, it locks
onto one Device Controller until the I/O program for that
device
is completed.
Then, a check is made to see which Device,Control-
ler has highest priority for the next block transfer.
SInce only
one I/O
program will be in progress as long as a
particular de-
vice is selected,
the Selector Channel is designed to facilitate
very high speed transfers.
The Selector Channel uses double-buf-
fering for
both data and
I/O program words.
(See figure 7-14.)
For data,
this permits device/channel transfers to overlap chan-
nel/memory transfers.
For I/O program words,
this permits
the
next
program word
to be fetched
from memory while
the current
word is active.
Both of these features contribute to the
speed
capablity.
In addition, the necessity to repeatedly fetch a DRT
entry for the address of the current I/O program word (as is done
by the Multiplexer Channel) is eliminated by including a
Program
Counter in
the Selector Channel.
The Program Counter is loaded
with the initial address contained in the DRT,
but is thereafter
incremented
(or altered
for jumps)
internally in the
Selector
Channel.
To
provide
software
compatibility
with
Multiplexer
Channel transfers,
the final
value
of the
Program Counter
is
automatically
restored in
the DRT at
the end
of the
program.
Software
cannot distinguish whether the transfer occurred by way
of the Multiplexer Channel or the Selector Channel.
The overall
Selector Channel operating sequence
is as
follows.
When
the Device
Controller is
commanded by
the CPU to
"start
I/O" ,
it ca uses the Se Ie ctor
Cha nne 1 to fe tch the
star t in g ad-
dress of the I/O program from the DRT (A).
This address is used
to fetch an
I/O program doubleword (B) and load
it into
either
the active control registers or,
during order prefetch, into the
buffers (C).
The
Program
Counter
is
incremented
after
each
fetch.
Control signals are issued to the r.evice Controller (D),
and (E),
if the command is a Read,
the Device
Controller reads
data into buffer A (or buffer B if A is full).
If the command is
a Write, the Device Controller writes data from buffer A (or buf-
fer B if A is empty) •
Meanwhile (F),
the Selector
Channel at-
tempts to
keep both
buffers full
for output or both
empty for
input,
by transmissions
to or from memory.
At the end
of the
block transfer,
the next
I/O program
word is fetched.
Repeat
back to step (B).
At the end of the I/O
program,
the Selector
Channel
stores its
Program Counter
contents into
the DRT (G).
(For a more detailed discussion, refer to paragraph 7-47.)
7-33. Multiplexer Channel Operations
A detailed
discussion of Multiplexer Channel operations
is con-
tained in paragraphs 7-34 through 7-46.
7-34.
INlTIALIZE~
When the CPU encounters an
SIO
instruction,
the CPU outputs a command word to the lOP Control Register.
(See
figure 7-10.)
The lOP relays this information to the Device Con-
troller (figure 7-15) via the lOP Bus.
The DEVNO on the lOP Bus
is compared with the internally wired device number.
A true re-
sult, together with the SO signal from the lOP, enables the IOCMD
7-28
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