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19
JTCK
JTMS
TAP
state
JTDI
High impedance
JTDO
Note: The shift operation of the data register for the shift register stage is right-shifted, therefore, the
output from JTDO is from the LSB side. Input to JTDI starts from the value to be set in LSB side.
Figure 19.4.4 DR Path Sequence
JTDI input is sampled at rise
of JTCK in "Shift-DR" state.
Don't Care
LSB value
JTDO is output at fall of
JTCK in "Shift-DR" state.
Setup data is set in the parallel output stage
at fall of JTCK in "Update-DR" state.
MSB value
Finished storing setup data in the shift
register stage of the selected data register.
19-11
19.4 Basic Operation of JTAG
Don't Care
High impedance
JTAG
Ver.0.10
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