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5
(2) ILEVEL (Interrupt Priority Level) (D5-D7 or D13-D15)
These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set
priority level 7 to disable interrupts from some internal peripheral I/O or priority levels 0-6 to
enable interrupts.
When an interrupt occurs, the interrupt controller resolves priority between this interrupt and
other interrupt sources based on ILEVEL settings and finally compares its priority with the IMASK
value to determine whether to forward an EI request to the CPU or keep it pending.
The table below shows the relationship between ILEVEL settings and the IMASK values at which
interrupts are accepted.
Table 5.3.1 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set
0 (ILEVEL="000")
1 (ILEVEL="001")
2 (ILEVEL="010")
3 (ILEVEL="011")
4 (ILEVEL="100")
5 (ILEVEL="101")
6 (ILEVEL="110")
7 (ILEVEL="111")
IMASK values at which interrupts are accepted
Accepted when IMASK is 1-7
Accepted when IMASK is 2-7
Accepted when IMASK is 3-7
Accepted when IMASK is 4-7
Accepted when IMASK is 5-7
Accepted when IMASK is 6-7
Accepted when IMASK is 7
Not accepted (interrupts disabled)
5-13
INTERRUPT CONTROLLER (ICU)
5.3 ICU-Related Registers
Ver.0.10
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