Transfer Operation - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

(7) Ring buffer mode

When ring buffer mode is selected, transfer begins from the transfer start address and after

performing transfers 32 times, control is recycled back to the transfer start address, from which

transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start

address must always be B'00000. The address increment operation in ring buffer mode is

described below.

When the transfer unit = 8 bits

The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are

incremented by one at a time. When as transfer proceeds the five low-order bits reach

B'11111, they are recycled to B'00000 by the next increment operation, thus returning to

the start address again.

When the transfer unit = 16 bits

The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are

incremented by two at a time. When as transfer proceeds the six low-order bits reach

B'111110, they are recycled to B'000000 by the next increment operation, thus returning to

the start address again.

When the source address has been set to be incremented, it is the source address that recycles

to the start address; when the destination address has been set to be incremented, it is the

destination address that recycles to the start address. If both source and destination addresses

have been set to be incremented, both addresses recycle to the start address. However, the start

address on either side must have their five low-order bits initially being B'00000.

During ring buffer mode, the transfer count register is ignored. Also, once DMA operation starts,

the counter operates in free-run mode, and the transfer continues until the transfer enable bit is

cleared to (to disable transfer).

Transfer count

Figure 9.3.4 Example of Address Increment Operation in 32-Channel Ring Buffer Mode

Transfer address

9.3 Functional Description of the DMAC

Transfer count

Transfer address