15
Read
BHW, BLW
DB0 - DB15
Write
BHW, BLW
DB0 - DB15
Note : Circles
Figure 15.2.2 Read/Write Timing (for Shortest-case External Access)
BCLK
A11 - A30
CS0, CS1
RD
"H"
WAIT
BCLK
A11 - A30
CS0, CS1
"H"
RD
WAIT
above indicate points at which signals are sampled.
EXTERNAL BUS INTERFACE
Read (2 cycles)
One wait cycle
"H"
Write (2 cycles)
One wait cycle
"H"
15-7
15.2 Read/Write Operations
Ver.0.10