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12
Table 12.1.1 Outline of Serial I/O
Item
Number of channels
Clock
Transfer mode
BRG count source
Data format
Baud rate
Error detection
Fixed period clock function When using SIO0, SIO1, SIO4 and SIO5 as UART, this function outputs a divided-
Note 1 : The maximum input frequency of external clock during CSIO mode is 1/16 of f(BCLK).
Note 2 : When f(BCLK) is selected as the BRG count source, the BRG set value is subject to limitations.
Content
CSIO/UART : 4 channels (SIO0, SIO1, SIO4, SIO5)
UART only : 2 channels (SIO2, SIO3)
During CSIO mode : Internal clock or external clock as selected (Note 1)
During UART mode : Internal clock only
Transmit half-duplex, receive half-duplex, transmit/receive full-duplex
f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (when internal peripheral clock selected) (Note 2)
f(BCLK) : Internal peripheral clock operating frequency
CSIO mode :
Data length = 8 bits (fixed)
Order of transfer = LSB first (fixed)
UART mode : Start bit = 1 bit
Character length = 7, 8, or 9 bits
Parity bit = Added or not added (when added, selectable between
Stop bit = 1 or 2 bits
Order of transfer = LSB first (fixed)
CSIO mode :
152 bits/sec to 2M bits/sec (at f(BCLK) = 20 MHz)
UART mode : 19 bits/sec to 156K bits/sec (at f(BCLK) = 20 MHz)
CSIO mode :
Overrun error only
UART mode : Overrun error, parity error, framing error (Occurrence of any of
these errors is indicated by an error sum bit)
by-2 BRG clock from the SCLK pin.
12-3
odd and even parity)
SERIAL I/O
12.1 Outline of Serial I/O
Ver.0.10
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