Typical Csio Transmit Operation - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

12.3.8 Typical CSIO Transmit Operation

The following shows a typical transmit operation in CSIO mode.

Transmit clock

Transmit enable bit

Transmit buffer

Transmit status bit

SIO transmit interrupt

Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit

Note 2 : When transmit interrupt is enabled (DMA transfer can also be requested at the same timing)

Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register"

interrupt request bit cleared

Note 4 : Transmit interrupt request is generated when transmission is enabled.

Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated

when the data is transferred from the transmit buffer to the transmit shift register and the transmit

buffer is thereby emptied.

Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once, with Transmit Interrupt Used)

Internal clock selected

buffer register

Set by a write to

transmit buffer

Interrupt request accepted

: Processing by software

12.3 Transmit Operation in CSIO Mode

External clock selected

Content of transmit buffer

transmit shift register

: Interrupt generation

completion of

transmission