Table of Contents
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3.1 Outline of Address Space ................................................................................ 3-2
3.2 Operation Modes ............................................................................................... 3-6
3.3 Internal ROM Area and Extended External Area ............................................ 3-8
3.3.1 Internal ROM Area ...................................................................................... 3-8
3.3.2 Extended External Area .............................................................................. 3-8
3.4 Internal RAM Area and SFR Area .................................................................... 3-9
3.4.1 Internal RAM Area ...................................................................................... 3-9
3.4.2 Special Function Register (SFR) Area ........................................................ 3-9
3.5 EIT Vector Entry .............................................................................................. 3-28
3.6 ICU Vector Table ............................................................................................. 3-29
3.7 Note about Address Space ............................................................................ 3-31
4.1 Outline of EIT..................................................................................................... 4-2
4.2 EIT Event ............................................................................................................ 4-3
4.2.1 Exception .................................................................................................... 4-3
4.2.2 Interrupt ...................................................................................................... 4-3
4.2.3 Trap ............................................................................................................ 4-3
4.3 EIT Processing Procedure ............................................................................... 4-4
4.4 EIT Processing Mechanism ............................................................................. 4-6
4.5 Acceptance of EIT Event .................................................................................. 4-7
4.6 Saving and Restoring the PC and PSW .......................................................... 4-8
4.7 EIT Vector Entry .............................................................................................. 4-10
4.8 Exception Processing .................................................................................... 4-11
4.8.1 Reserved Instruction Exception (RIE) ....................................................... 4-11
4.8.2 Address Exception (AE) ............................................................................ 4-13
4.9 Interrupt Processing ....................................................................................... 4-15
4.9.1 Reset Interrupt (RI) ................................................................................... 4-15
4.9.2 System Break Interrupt (SBI) .................................................................... 4-16
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Table of Contents
