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8
____
P71 (WAIT)
__
P70 (BCLK / WR)
____
P73 (HACK)
P74 (RTDTXD)
P76 (RTDACK)
P82 (TXD0)
P85 (TXD1)
P93 - P97 (TO16-TO20)
P100 - P107 (TO8-TO15)
P110 - P117 (TO0-TO7)
P160 - P167 (TO21 - TO28)
P174 (TXD2)
P176 (TXD3)
P180 - P187 (TO29-TO36)
P200 (TXD4)
P202 (TXD5)
P210 - P217 (TO37-TO44)
P220 (CTX)
Note :
denotes pins.
Figure 8.4.3 Port Peripheral Circuit Diagram (3)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
Port output
Data bus
(DB0 - DB15)
Operation
mode register
WAIT
Data bus
Port output
(DB0 - DB15)
Operation
mode register
Peripheral
function input
8-33
8.4 Port Peripheral Circuits
Direction
register
latch
Input function
enable
Direction
register
latch
Input function
enable
Ver.0.10
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