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10
(3) Single-shot PWM output mode (without correction function)
In single-shot PWM output mode, the timer uses two reload registers to generate a waveform
with a given duty cycle only once.
When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by
writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0
register value into the counter synchronously with the count clock, letting the counter start
counting down. The first time the counter underflows, the reload 1 register value is loaded into the
counter letting it continue counting. Then when the counter underflows next time, it stops. The
valid count values are the (reload 0 register set value + 1) and (reload 1 register set value + 1)
each. To stop the timer in software, disable count by writing to the enable bit. The timer stops at
the same time count is disabled (and not in synchronism with PWM output period).
The F/F output waveform in single-shot PWM output mode is inverted (F/F output levels change
from low to high, or vice versa) upon each underflow. (Unlike in PWM output mode, F/F output is
not inverted at counter startup.) An interrupt can be generated when the counter underflows
second time after being enabled.
(4) Continuous output mode (without correction function)
In continuous output mode, the timer counts down clock pulses starting from the set value of the
counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter,
this operation is repeated each time the counter underflows, thus generating consecutive pulses
in width of (reload 0 register set value + 1).
When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable
bit in software or by TID2 underflow/overflow signal), it starts counting down from the counter's
set value synchronously with the count clock and when the minimum count is reached, generates
an underflow. This underflow causes the counter to be reloaded with the content of reload 0
register and start counting again. Thereafter, this operation is repeated each time an underflow
occurs. To stop the counter, disable count by writing to the enable bit in software.
The F/F output waveform in continuous output mode is inverted at startup and upon underflow,
generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated
each time the counter underflows.
10.9 TOM (Output-related 16-bit Timer)
10-206
MULTIJUNCTION TIMERS
Ver.0.10
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