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9
DMA5-9 Interrupt Request Status Register (DM59ITST)
D0
D
Bit Name
0 - 2
No functions assigned
3
DMITST9 (DMA9 interrupt request status)
4
DMITST8 (DMA8 interrupt request status)
5
DMITST7 (DMA7 interrupt request status)
6
DMITST6 (DMA6 interrupt request status)
7
DMITST5 (DMA5 interrupt request status)
W =
: Only writing a 0 is effective; when you write a 1, the previous value is retained.
The DMA5-9 Interrupt Request Status Register lets you know the status of interrupt requests in
channels 5-9. If the DMAn interrupt request status bit (n = 5 to 9) is set to 1, it means that a DMAn
interrupt request in the corresponding channel has been generated.
DMITSTn (DMAn interrupt request status) bit (n = 5 to 9)
[Setting the DMAn interrupt request status bit]
This bit can only be set in hardware, and cannot be set in software.
[Clearing the DMAn interrupt request status bit]
This bit is cleared by writing a 0 in software.
Note: The DMAn interrupt request status bit cannot be cleared by writing a 0 to the
"Interrupt cause bit" of the DMA Interrupt Control Register that the interrupt
controller has.
When writing to the DMA5-9 Interrupt Request Status Register, be sure to set the bits you want to
clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in
software, and retain the value they had before you wrote.
1
2
3
DMITST9 DMITST8 DMITST7 DMITST6 DMITST5
9-22
9.2 DMAC Related Registers
<Address: H'0080 0408>
4
5
6
Function
0 : No interrupt request
1 : Interrupt requested
DMAC
D7
<When reset : H'00>
R
W
0
—
Ver.0.10
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