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10
When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by
writing to the enable bit in software or by external input), it loads the reload 0 register value into
the counter synchronously with the count clock letting the counter start counting down. The first
time the counter underflows, the reload 1 register value is loaded into the counter letting it
continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register
values alternately each time an underflow occurs.
The F/F output waveform in PWM output mode is inverted at count startup and upon each
underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not
in synchronism with PWM output period). An interrupt can be generated when the counter
underflows every other time (second time, fourth time, and so on) after being enabled.
(4) Single-shot output mode (without correction function)
In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value +
1) only once and stops without performing any operation.
When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in
software or by external input), it loads the content of reload 0 register into the counter
synchronously with the count clock, letting the counter start counting. The counter counts down
clock pulses and stops when it underflows after reaching the minimum count.
The F/F output waveform in single-shot output mode is inverted at startup and upon underflow,
generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once.
Also, an interrupt can be generated when the counter underflows.
(5) Delayed single-shot output mode (without correction function)
In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set
value + 1) only once, with the output delayed by an amount of time equal to (counter set value +
1) and then stops without performing any operation.
When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable
bit in software or by external input), it starts counting down from the counter's set value
synchronously with the count clock. The first time the counter underflows, the reload 0 register
value is loaded into the counter causing it to continue counting down, and the counter stops when
it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted when the counter
underflows first time and next, generating a single-shot pulse waveform in width of (reload 0
register set value + 1) only once, with the output delayed by an amount of time equal to (first set
value of counter + 1). Also, an interrupt can be generated when the counter underflows first time
and next.
10.4 TIO (Input/Output-related 16-bit Timer)
10-103
MULTIJUNCTION TIMERS
Ver.0.10
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