Table of Contents
Advertisement
SERIAL I/O
12
12.2 Serial I/O Related Registers
In UART mode, the serial I/O divides the internal BCLK using the clock divider. Next, it divides the
resulting clock by (BRG set value + 1) according to the BRG set value and then by 16, which
results in generating a transmit/receive shift clock.
When using SIO0, SIO1, SIO4 or SIO5 in UART mode, you can choose the relevant port (P84,
P87, P65 or P66) to function as the SCLKO pin, so that a divided-by-2 BRG output clock can be
output from the SCLKO pin.
When using the internal clock (internally clocked CSIO or UART mode), with f(BCLK) selected as
the BRG count source, make sure that during CSIO mode, the transfer rate does not exceed 2
Mbits per second, and that during UART mode, BRG is equal to or greater than 7.
12-27
Ver.0.10
Advertisement
Table of Contents
