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Page
Item
717
18.2.8 DDC Switch Register (DDCSWR)
719
18.3.1 I
720 to
18.3.2 Master Transmit Operation
722
722 to
18.3.3 Master Receive Operation
724
731, 732
18.3.9 Sample Flowcharts
734 to
18.3.10 Initialization of Internal State
736
736, 737,
18.4 Usage Notes
739, 740
740 to
743
745
19.1.1 Features
753
19.2.3 A/D Control Register (ADCR)
2
C Bus Data Format
Revisions
(See Manual for Details)
Description of bits 7 to 4 amended
Bits 3 to 0 amended and Note 2
added
Description of CLR3-0 added
Description amended
2
C Bus Data Formats
Figure 18-3 I
2
(I
C Bus Formats)
Formatless description deleted
Description amended
Description amended
Figure 18-8 Example of Master
Receive Mode Operation Timing
(MLS = WAIT = ACKB = 0)
amended
Figure 18-14 Flowchart for Master
Transmit Mode (Example) amended
Figure 18-15 Flowchart for Master
Receive Mode (Example) amended
Added
2
Table 18-6 I
C Bus Timing (SCL
and SDA Output) amended
Table 18-7 Permissible SCL Rise
Time (t
) Values ø = 25 MHz added
Sr
to time indication
2
Table 18-8 I
C Bus Timing (with
Maximum Influence of t
amended
Note on ICDR Read at End of
Master Reception added
Notes on Start Condition Issuance
for Retransmission added
2
Notes on I
C Bus Interface Stop
Condition Instruction Issuance
added
Conversion time amended
Bit 3 and 2 (conversion time)
amended
/t
)
Sr
Sf
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