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Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 16-23 Receive Data Sampling Timing in Asynchronous Mode
Thus the reception margin in asynchronous mode is given by formula (1) below.
1
M = | (0.5 –
2N
Where M : Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
1
M = (0.5 –
2 × 16
= 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
652
16 clocks
8 clocks
7
Start bit
) – (L – 0.5) F –
) × 100%
15 0
D0
| D – 0.5 |
(1 + F) | × 100%
N
7
15 0
... Formula (1)
... Formula (2)
D1
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