Hitachi H8S/2633 Hardware Manual page 598

ø
TCNT
Overflow signal
(internal signal)
OVF
15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At
the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR
is set to 1, an internal reset signal is generated for the entire H8S/2633 Series chip. Figure 15-7
shows the timing in this case.
ø
TCNT
Overflow signal
(internal signal)
WOVF
WDTOVF signal
Internal reset
signal
H'FF
Figure 15-6 Timing of Setting of OVF
H'FF
Figure 15-7 Timing of Setting of WOVF
H'00
H'00
132 states
518 states (WDT0)
515/516 states (WDT1)
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