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7.5.9
Byte Access Control
When 16-bit DRAMs are connected, the 2 CAS method can be used as the control signal required
for byte access.
Figure 7-19 shows the 2 CAS method control timing. Figure 7-20 shows an example of connecting
DRAM in high-speed page mode.
When all areas selected as DRAM space are set as 8-bit space, the LCAS pin functions as an I/O
port.
A23 to A0
CSn (RAS)
Byte control
LCAS
HWR (WE)
Note: n= 2 to 5
Figure 7-19 2 CAS Method Control Timing (For High Byte Write Access)
When using DRAM EDO page mode, either use OE to control the read data or, as shown in Figure
7-20, select RAS up mode. Figure 7-21 is an example of DRAM connection in EDO page mode
when OES=1.
T
p
ø
CAS
T
T
r
c1
row
column
T
c2
179
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