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25.3.5
Timing of On-Chip Supporting Modules
Table 25-9 lists the timing of on-chip supporting modules.
Table 25-9 Timing of On-Chip Supporting Modules
Condition A: V
CC
V
= 3.3 V to AV
ref
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Condition B: V
CC
V
= 3.3 V to AV
ref
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Item
I/O port
Output data delay
time
Input data setup
time
Input data hold
time
PPG
Pulse output delay
time
TPU
Timer output
delay time
Timer input setup
time
Timer clock input
setup time
Timer
clock
pulse
width
906
= PLLV
= 3.0 V to 3.6 V, PV
CC
, V
CC
SS
= PLLV
= 3.0 V to 3.6 V, PV
CC
, V
CC
SS
Symbol
t
PWD
t
PRS
t
PRH
t
POD
t
TOCD
t
TICS
t
TCKS
Single
t
TCKWH
edge
Both
t
TCKWL
edges
= 3.0 V to 5.5 V, AV
CC
= AV
= 0 V, ø = 32.768 kHz*, 2 to 16 MHz,
SS
= 4.5 V to 5.5 V, AV
CC
= AV
= 0 V, ø = 32.768 kHz*, 2 to 25 MHz,
SS
Condition A
Min
Max
—
60
40
—
40
—
—
60
—
60
40
—
40
—
1.5
—
2.5
—
= 3.3 V to 5.5 V,
CC
= –40°C to +85°C (wide-range
a
= 3.3 V to 5.5 V,
CC
= –40°C to +85°C (wide-range
a
Condition B
Min
Max
Unit
—
40
ns
25
—
25
—
—
40
ns
—
40
ns
25
—
25
—
ns
1.5
—
t
cyc
2.5
—
Test Conditions
Figure 25-20
Figure 25-21
Figure 25-22
Figure 25-23
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