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RES, MRES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000,
(3) = H'000002)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
Start address ((5) = (2) (4))
(6)
First program instruction
4.2.4
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.2.5
State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively,
and all modules except the DMAC and DTC, enter module stop mode. Consequently, on-chip
supporting module registers cannot be read or written to. Register reading and writing is enabled
when module stop mode is exited.
Figure 4-3 Reset Sequence (Modes 6 and 7)
Vector
Internal
fetch
processing
(1)
(3)
High
(2)
(4)
Prefetch of
first program
instruction
(5)
(6)
85
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