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To transmit data continuously:
(6) Before the rise of the 9th transmit clock pulse for the data being transmitted, clear the IRIC
flag to 0 and then write the next transmit data to ICDR.
(7) When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of
the 9th transmit clock pulse. At the same time, the next transmit data written into ICDR
(ICDRT) is transferred to ICDRS, the TDRE internal flag is set to 1, and then the next frame is
transmitted in synchronization with the internal clock.
Data can be transmitted continuously by repeating steps (6) and (7).
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TDRE
IRIC
ICDRT
ICDRS
User processing
Figure 18-7 Example of Master Transmit Mode Continuous Transmit Operation Timing
18.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data. The reception procedure and operations in
master receive mode are described below.
(1) Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Also clear the
ACKB bit in ICSR to 0 (acknowledge data setting).
722
1
2
3
Bit 7
Bit 6
Bit 5
Data 1
Data 2
Data 1
ICDR write
[6] IRIC clearance
(MLS = WAIT = 0)
4
5
6
7
Bit 4
Bit 3
Bit 2
Bit 1
Data 1
[6] ICDR write
8
9
1
2
Bit 0
Bit 7
Bit 6
Data 2
[7]
A
Interrupt
request
generation
[7]
Data 2
[6] IRIC clearance
[6] ICDR write
3
Bit 5
Data 3
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