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18.3.8
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 18-13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or
D
SDA input
signal
System clock
Sampling
clock
18.3.9
Sample Flowcharts
Figures 18-14 to 18-17 show sample flowcharts for using the I
730
C
Q
Latch
period
Figure 18-13 Block Diagram of Noise Canceler
C
D
Q
Latch
2
C bus interface in each mode.
Internal
Match
SCL or
detector
SDA
signal
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