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(2) When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to determine the end of
reception, the IRIC flag in ICCR must be cleared beforehand.
(3) The master device drives SDA at the 9th receive clock pulse to return an acknowledge signal.
When one frame of data has been received, the IRIC flag in ICCR is set to 1 at the rise of the
9th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to
the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive
operation continues. If reception of the next frame ends before the ICDR read/IRIC flag
clearing in (4) is performed, SCL is automatically fixed low in synchronization with the
internal clock.
(4) Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Data can be received continuously by repeating steps (3) and (4). As the RDRF internal flag is
cleared to 0 when reception is started after initially switching from master transmit mode to master
receive mode, reception of the next frame of data is started automatically. To halt reception, the
TRS bit must be set to 1 before the rise of the receive clock for the next frame.
To halt reception, set the TSR bit to 1, read ICDR, then write 0 to BBSY and SCP in ICCR. This
changes SDA from low to high when SCL is high, and generates the stop condition.
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