Hitachi H8S/2633 Hardware Manual page 523

Next Data Registers H and L (NDRH, NDRL)

NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output.

During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in

PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH

and NDRL addresses differ depending on whether pulse output groups have the same output

trigger or different output triggers. For details see section 12.2.4, Notes on NDR Access.

NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are

not initialized in software standby mode.

Notes on NDR Access

The NDRH and NDRL addresses differ depending on whether pulse output groups have the same

output trigger or different output triggers.

Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the

same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3

and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be

modified and are always read as 1.

Address H'FE2C

Initial value :

Address H'FE2E

Initial value :

If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address

is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F

consists entirely of reserved bits that cannot be modified and are always read as 1. However, the

H8S/2633 Series has no output pins corresponding to pulse output groups 0 and 1.