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19.2.2
A/D Control/Status Register (ADCSR)
Bit
:
Initial value
:
R/W
:
R/(W)*
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing conditions]
•
When 0 is written to the ADF flag after reading ADF = 1
•
When the DTC is activated by an ADI interrupt and ADDR is read
1
[Setting conditions]
•
Single mode: When A/D conversion ends
•
Scan mode: When A/D conversion ends on all specified channels
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE
Description
0
A/D conversion end interrupt (ADI) request disabled
1
A/D conversion end interrupt (ADI) request enabled
750
7
6
ADF
ADIE
0
0
R/W
5
4
ADST
SCAN
0
0
R/W
R/W
3
2
CH3
CH2
0
0
R/W
R/W
1
0
CH1
CH0
0
0
R/W
R/W
(Initial value)
(Initial value)
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