Hitachi H8S/2633 Hardware Manual page 202

Precharge State Control

When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is

therefore necessary to insert 1 T

can be changed from 1 state to 2 states. Set the appropriate number of T

according to the type of DRAM connected and the operation frequency of the LSI. Figure 7-16

shows the timing when T

Setting the TPC bit to 1 also sets the refresh cycle T

Note: n= 2 to 5

state when accessing DRAM space. By setting the TPC bit of the

is set for 2 states.

Figure 7-16 Timing With Two Precharge Cycles

to 2 states.