Hitachi H8S/2633 Hardware Manual page 230

Bus Arbitration

The H8S/2633 Series has a bus arbiter that arbitrates bus master operations.

There are two bus masters, the CPU, DTC, and DMAC which perform read/write operations when

they have possession of the bus. Each bus master requests the bus by means of a bus request

signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by

means of a bus request acknowledge signal. The selected bus master then takes possession of the

bus and begins its operation.

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is canceled.

The order of priority of the bus masters is as follows:

An internal bus access by an internal bus master, external bus release, and refresh can be executed

in parallel.

In the event of simultaneous external bus release request, refresh request, and internal bus master

external access request generation, the order of priority is as follows:

(High) Refresh > External bus release > External access by internal bus master (Low)

(High) Refresh > External bus release (Low)

(High) External bus release > External access by internal bus master (Low)