Hitachi H8S/2633 Hardware Manual page 920

Item
TMR Timer output delay
time
Timer reset input
setup time
Timer clock input
setup time
Timer
clock
pulse
width
WDT0 Overflow output
delay time
WDT1 Buzz output delay
time
PWM Pulse output delay
time
SCI Input
clock
cycle
Input clock pulse
width
Input clock rise
time
Input clock fall
time
Transmit data
delay time
Receive data setup
time (synchronous)
Receive data hold
time (synchronous)
A/D Trigger input setup
converter time
Note: * Only available I/O port, TMR, WDT0, and WDT1.
Symbol
t
TMOD
t
TMRS
t
TMCS
Single t
TMCWH
edge
Both t
TMCWL
edges
t
WOVD
t
BUZD
t
PWOD
Asynchro- t
Scyc
nous
Synchro-
nous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
Condition A Condition B
Min Max Min
— 60 —
40 — 25
40 — 25
1.5 — 1.5
2.5 — 2.5
— 60 —
— 60 —
— 60 —
4 — 4
6 — 6
0.4 0.6 0.4
— 1.5 —
— 1.5 —
— 60 —
60 — 40
60 — 40
60 — 40
Max Unit Test Conditions
40 ns Figure 25-24
— ns Figure 25-26
— ns Figure 25-25
— t
cyc
—
40 ns Figure 25-27
40 ns Figure 25-28
40 ns Figure 25-29
— t Figure 25-30
cyc
—
0.6 t
Scyc
1.5 t
cyc
1.5
40 ns Figure 25-31
—
—
— ns Figure 25-32
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