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Hitachi H8S/2633 Hardware Manual page 84

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2.8
Processing States
2.8.1
Overview
The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the
processing states. Figure 2-15 indicates the state transitions.
Processing
states
Note: * The power-down state also includes a medium-speed mode, module stop mode,
subactive mode, subsleep mode, and watch mode.
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Power-down state
CPU operation is stopped
to conserve power.*
Figure 2-14 Processing States
Sleep mode
Software standby
mode
Hardware standby
mode
57

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