Advertisement
2
Bit 7—I
C Bus Interface Enable (ICE): Selects whether or not the I
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Bit 7
ICE
Description
2
0
I
C bus interface module disabled, with SCL and SDA signal pins
set to port function
2
I
C bus interface module internal states initialized
SAR and SARX can be accessed
2
1
I
C bus interface module enabled for transfer operations (pins SCL and SCA are driving
the bus)
ICMR and ICDR can be accessed
2
Bit 6—I
C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I
bus interface to the CPU.
Bit 6
IEIC
Description
0
Interrupts disabled
1
Interrupts enabled
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I
TRS selects whether the I
In master mode with the I
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
2
C bus interface operates in master mode or slave mode.
2
C bus interface operates in transmit mode or receive mode.
2
C bus format, when arbitration is lost, MST and TRS are both reset by
2
C bus interface is to be
2
C bus interface module is halted and its
(Initial value)
2
C
(Initial value)
705
Advertisement
