Hitachi H8S/2633 Hardware Manual page 917

ø
A23 to A0
CS7 to CS0
AS
RD
(read)
D15 to D0
(read)
HWR to LWR
D15 to D0
(write)
DACK0, DACK1
Figure 25-17 DMAC Single Address Transfer Timing / Three-State Access
ø
TEND0, TEND1
904
T
1
t
DACD1
T
1
t
TED
Figure 25-18 DMAC TEND Output Timing
T T
2 2
T orT
2 3
t
DACD2
t
TED