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14.4
Operation
A PWM waveform like the one shown in figure 14-3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (T
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (T
output pulses. Figure 14-4 shows the types of waveform output available.
t
f
Basic cycle
(T × 64 or T × 256)
t
L
Table 14-4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 14-4 indicates the range of DADR settings that give an output
waveform like the one in figure 14-3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
558
1 conversion cycle
(T × 2
14
(= 16384))
T: Resolution
= ∑ t
T
L
n = 1
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 14-3 PWM D/A Operation
) of the low (0) pulses output in one
L
m
(when OS = 0)
Ln
) of the high (1)
H
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