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Hitachi H8S/2633 Hardware Manual page 338

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9.3.5
Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 9-5 lists the register information in normal mode and figure 9-6 shows memory mapping in
normal mode.
Table 9-5
Register Information in Normal Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
SAR
Abbreviation
SAR
DAR
CRA
CRB
Figure 9-6 Memory Mapping in Normal Mode
Function
Designates source address
Designates destination address
Designates transfer count
Not used
Transfer
DAR
313

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