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14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) .............................. 551
14.2.3 PWM D/A Control Register (DACR)................................................................... 552
14.2.4 Module Stop Control Register B (MSTPCRB) .................................................... 554
14.3 Bus Master Interface .......................................................................................................... 555
14.4 Operation............................................................................................................................ 558
Section 15 Watchdog Timer
15.1 Overview............................................................................................................................ 563
15.1.1 Features ................................................................................................................. 563
15.1.2 Block Diagram...................................................................................................... 564
15.1.3 Pin Configuration.................................................................................................. 566
15.1.4 Register Configuration.......................................................................................... 566
15.2 Register Descriptions ......................................................................................................... 567
15.2.1 Timer Counter (TCNT)......................................................................................... 567
15.2.2 Timer Control/Status Register (TCSR) ................................................................ 567
15.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 572
15.2.4 Pin Function Control Register (PFCR) ................................................................. 573
15.2.5 Notes on Register Access ..................................................................................... 574
15.3 Operation............................................................................................................................ 576
15.3.1 Watchdog Timer Operation .................................................................................. 576
15.3.2 Interval Timer Operation ...................................................................................... 578
15.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 578
15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 579
15.4 Interrupts ............................................................................................................................ 580
15.5 Usage Notes ....................................................................................................................... 580
15.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 580
15.5.2 Changing Value of CKS2 to CKS0 ...................................................................... 581
15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 581
15.5.4 System Reset by WDTOVF Signal ...................................................................... 581
15.5.5 Internal Reset in Watchdog Timer Mode.............................................................. 581
Section 16 Serial Communication Interface (SCI, IrDA)
16.1 Overview............................................................................................................................ 583
16.1.1 Features ................................................................................................................. 583
16.1.2 Block Diagram...................................................................................................... 586
16.1.3 Pin Configuration.................................................................................................. 586
16.1.4 Register Configuration.......................................................................................... 587
16.2 Register Descriptions ......................................................................................................... 589
16.2.1 Receive Shift Register (RSR) ............................................................................... 589
16.2.2 Receive Data Register (RDR)............................................................................... 589
16.2.3 Transmit Shift Register (TSR).............................................................................. 590
16.2.4 Transmit Data Register (TDR).............................................................................. 590
16.2.5 Serial Mode Register (SMR) ................................................................................ 591
.............................................................................................. 563
........................................ 583
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